Monday, September 19, 2005

How to seal ESD shielding bags?

How important is it to fully close a static shielding bag that contains static-sensitive components? Is it good enough to fold and tape the bag (with what kind of tape?), should a double-fold be used, or are the zipper-style bags better?

A shielding bag gives best protection when closed and fully surrounding the components or board within. It has two functions - 1) to shield against electrostatic field, and 2) to protect against direct ESD to the ESD susceptible parts inside. A typical bag is a laminated material having some insulating layers to stop ESD curent flow through the material, and a metallisation layer to provide electrostatic field shielding. Inner and outer surfaces should be static dissipative (or in some cases may be conductive) to prevent charge build-up.

If you fold the bag do not crease it as this may break the metallisation layer and impair the protection. A loose single fold, held by a label or tape is fine. However, remember you don't want to be using ordinary high charging tapes within an ESD Protected Area. Avoid having component leads puncture the bag.

Never staple a bag as this gives a route for ESD to pass through and make contact with components inside.

A zipper style bag is fine.

A very useful article on ESD bags is given here

Wednesday, September 07, 2005

What level of ESD will damage parts?

>> I have currently been tasked with trying to improve the ESD standards
>> within our manufacturing facility.
>> One question which has arisen which I cannot find an answer to is this. Is
>> there a level of ESD at which it is generally accepted that on or above
>> this level, significant damage will occur to electronic parts?
>> We are shortly going to be going through the process in question, and
>> measuring the charges and voltages which are created whilst working. It
>> would help us greatly to know if there is a "safe" level of ESD which can
>> be allowed to occur.

The ESD susceptibility of devices depends on the particular component. Each has an "ESD withstand voltage" determined during QA tests. Virtually all semiconductor components have been tested using "Human Body Model" (HBM), some have also been tested using "Machine Model" (MM) or "Charged Device Model" (CDM). Unfortunately many manufacturers do not make this information readily available to users. As a result we end up relying on guesswork for the susceptibility of components. A rough guide is given in our ESD Guide

The ESD standards such as 61340-5-1 are designed to protect devices down to 100 V HBM. For many processes this will be adequate. Some types of components are more susceptible than this (< 100V HBM) and special measures and care are then required.

It is not easy to assess ESD risk in a process. The usual way is to measure electrostatic fields and potentials in the region of the ESD susceptible parts. The 61340-5-1 standard recommends that electrostatic fields should not exceed 10,000 V/m and potentials (voltages) should not exceed 100 V. Note that a 1,000 V/m field could be a 10,000 V source at 1m, or a 100 V source at 1 cm distance etc. In practice I regard the field criterion as the most useful.

The best approach is to remove all non-essential insulators and electrostatic field sources in the ESD Protected Area (EPA). Any essential insulators or other sources may then be assessed for ESD risk, and appropriate ameliorating action (e.g. use of ionisers) taken.